1. Field of the Invention
The present invention relates to a signal processing method and a signal processing circuit, and particularly relates to a method and a circuit for automatically adjusting a phase of a sampling clock used when sampling an analog signal and converting the signal to a digital signal.
2. Description of Related Art
In a digital image display apparatus and the like, an analog-to-digital convertor samples (quantizes) RGB (Red-Green-Blue) signals being image data by use of a sampling clock, and thereby converts the signals to digital image signals. Here, generation of the sampling clock for the RGB signals is triggered by their synchronizing signals (a horizontal synchronizing signal and a vertical synchronizing signal). However, under the condition that the delays (input timings) of RGB signals and their synchronizing signals are not the same, the following problem has occurred. Specifically, sampling is not performed appropriately by use of a sampling clock generated in response to such synchronizing signals as triggers, and consequently a blurred image is obtained when the resultant digital image signals are displayed.
Descriptions will hereinafter be given of related techniques [1] and [2] for dealing with the problem.
Related Technique [1]: FIGS. 7 to 10
A signal processing circuit 1a shown in FIG. 7 includes: an analog-to-digital convertor 10 which samples an inputted analog signal SA to convert the signal to a digital signal SD; a clock generator 20 which sequentially generates sampling clocks C0 to Cn having different phases in response to a synchronizing signal Ssync of the analog signal SA as a trigger, and provides these sampling clocks to the convertor 10; a clock controller 30 which provides frequency data Cf and phase data Cp (phases P0 to Pn of the respective clocks C0 to Cn) for informing the generator 20 of the frequency and the phases of the sampling clocks; and an effective image area start/end point detector 40 which operates with the sampling clocks C0 to Cn and the synchronizing signal Ssync, detects a start point HcS and an end point HcE of the effective image area of the analog signal SA by comparing the signal level of the digital signal SD with a predetermined threshold value Th, and provides these points to the clock controller 30.
Here, when receiving the synchronizing signal Ssync, the clock controller 30 determines a frequency common to the sampling clocks C0 to Cn on the basis of previously held parameters (such as the number of output pixels of the digital signal SD) and outputs the frequency as the frequency data Cf. In addition, the clock controller 30 finally determines a phase suitable for sampling among the clock phases P0 to Pn on the basis of the effective image area start points HcS and end points HcE detected on the operational conditions with the respective sampling clocks C0 to Cn.
Furthermore, as shown in FIG. 8, the effective image area start point HcS is a point (timing) where the analog signal SA first enters the effective image area after the input of the synchronizing signal Ssync, and the end point HcE is a point where the analog signal SA has just gone away from the effective image area. Accordingly, these points HcS and HcE can be detected by monitoring the signal level of the digital signal SD.
Descriptions will hereinafter be given of the detailed operations of the above signal processing circuit 1a with reference to FIGS. 9 and 10.
Now, it is assumed that the analog signal SA shown in FIG. 9 is sampled by use of sampling clocks C0 to C7 (clocks being out of phase with each other by a time obtained by dividing a clock cycle by 8).
In this case, with regard to the sampling clocks C0 to C3, the signal level (unillustrated) of the digital signal SD outputted from the analog-to-digital convertor 10 exceeds a threshold value Th for the first time at the rising timing of the s-th pulse PLs from the first. Then, the signal level of the digital signal SD falls below the threshold value Th at the rising timings of the pulses subsequent to the e-th (e>s) pulse PLe from the first.
On the other hand, with regard to the sampling clocks C4 to C7, the signal level of the digital signal SD exceeds the threshold value Th for the first time at the rising timing of a pulse PLs-1. Then, with regard to the sampling clock C4, the signal level of the digital signal SD falls below the threshold value Th at the rising timings of the pulses subsequent to the pulse PLe, as in the sampling clocks C0 to C3. Meanwhile, with regard to the sampling clocks C5 to C7, the signal level of the digital signal SD falls below the threshold value Th at the rising timings of the pulses subsequent to a pulse PLe-1.
Therefore, as shown in FIG. 10, the effective image area start/end point detector 40 sets the effective image area start point HcS to the pulse PLs for the sampling clocks C0 to C3 while setting the start point HcS to the pulse PLs-1 for the sampling clocks C4 to C7. In addition, the effective image area start/end point detector 40 sets the effective image area end point HcE to the pulse PLe for the sampling clocks C0 to C4 while setting the end point HcE to the pulse PLe-1 for the sampling clocks C5 to C7.
Upon receiving the start points HcS and the end points HcE, the clock controller 30 firstly calculates the difference between each pair of start and end points “HcE−HcS” (that is, the number of samples included in each digital signal SD). The point differences “HcE−HcS” thus obtained are not equal to one another. Specifically, the point difference in the sampling clock C4, shown in the shaded area in the drawing, is greater by “1” pulse than those in the other sampling clocks C0 to C3 and C5 to C7, namely, the number of samples for C4 are different from those for C0 to C3 and C5 to C7.
Hence, the clock controller 30 provides the clock generator 20 with the center phase of the sampling clocks C0 to C3 and C5 to C7, which are expected to have the correct point difference “HcE−HcS,” that is, the phase P0 of the sampling clock C0, as the phase data Cp.
In this manner, the signal processing circuit 1a can automatically adjust the phase of a sampling clock used for the sampling of the analog signal SA (refer to Patent Document 1, for example).
However, such a signal processing circuit has a problem that an adjusted phase of a sampling clock varies depending on the set value of the threshold value Th.
For example, assume that the analog signal SA shown in FIG. 11 is inputted. In this case, the results of adjusting the phase of a sampling clock are different between when using a threshold value Tha and when using a threshold value Thb which is set smaller than the threshold value Tha.
In other words, even though the same analog signal SA is sampled by use of the sampling clocks C0 to C7 respectively having the same phases in both the cases where the threshold values Tha and Thb are used, the clock controller 30 selects different phases in these cases as shown in FIG. 12. Specifically, the clock controller 30 selects the phase P1 (the center phase of the sampling clocks C0 to C3 and C7, which are expected to have the correct point difference “HcE−HcS”) of the sampling clock C1 when the threshold value Tha is used while selecting the phase P7 (the center phase of the sampling clocks C0 to C2 and C4 to C7, which are expected to have the correct point difference “HcE−HcS”) of the sampling clock C7 when the threshold value Thb is used.
To deal with the problem, the related technique [2] has been proposed as follows.
Related Technique [2]: FIGS. 13 to 17
A signal processing circuit 1b shown in FIG. 13 includes a frequency informing unit 50 and a phase determination unit 60 instead of the clock controller 30 and the effective image area start/end point detector 40, which are shown in FIG. 7.
Here, the frequency informing unit 50 determines a frequency common to the sampling clocks C0 to Cn on the basis of parameters previously held when receiving the synchronizing signal Ssync, and outputs the frequency as the frequency data Cf, similarly to the clock controller 30.
Furthermore, the phase determination unit 60 has: a maximum difference detector 61 which detects maximum values D0_max to Dn_max (hereinafter, referred to as the maximum differences, and may be collectively called a symbol D_max) of absolute differences between each adjacent two signal levels in each digital signal SD sequentially sampled by the sampling clocks C0 to Cn; and a phase informing unit 62b which provides the clock generator 20 with the phase of the sampling clock, from which the maximum value has been obtained, among these maximum differences D0_max to Dn_max, as the phase data Cp.
With regard to the operations, first, the phase informing unit 62b sequentially provides the clock generator 20 with the clock phases P0 to P7 first, and generates the sampling clocks C0 to C7, similarly to the clock controller 30 shown in FIG. 7.
The analog-to-digital convertor 10 operates with the sampling clocks C0, C1, . . . , C4, . . . , and C7 as shown in FIG. 14, sequentially converts the analog signal SA to digital signals SD0_1, SD0_2, . . . (hereinafter, they may collectively be called the symbol SD0), SD1_1, SD1_2, . . . (hereinafter, they may collectively be called the symbol SD1), . . . , SD4_1, SD4_2, . . . (hereinafter, they may collectively be called the symbol SD4), . . . , and SD7_1, SD7_2, . . . (hereinafter, they maybe collectively called the symbol SD7), and provides the signals to the maximum difference detector 61.
Here, an optimum phase of the sampling clock is one which can capture the peak value of the analog signal SA. Therefore, the absolute difference between adjacent signal levels in the digital signal SD becomes larger as sampled by a sampling clock with a more appropriate phase. Hence, the maximum difference detector 61 detects absolute differences for all the signal levels of the digital signals SD0 to SD7.
In other words, as shown in FIG. 15, first, the maximum difference detector 61 detects a difference obtained by the sampling clock C0 between the signal levels of the digital signals SD0_1 and SD0_2, which are adjacent to each other, and detects the absolute difference DA0. Similarly, the maximum difference detector 61 detects the absolute differences DA1 to DA7 of the digital signals SD1 to SD7 obtained respectively by use of the sampling clocks C1 to C7. The maximum difference detector 61 executes the process for all the signal levels of the digital signals SD0 to SD7.
In other words, as shown in FIG. 16, the maximum difference detector 61 detects absolute differences DAn(i), Dan(i+1), DAn(i+2), . . . (i is a natural number) for the whole analog signal SA. The maximum difference detector 61 then provides the phase informing unit 62b with the largest DAn(i) among the illustrated absolute differences DAn(i) to DAn(i+2), for example, as the maximum difference Dn_max.
Assuming that D0_max is now the largest among the absolute differences D0_max to D7_max as shown in FIG. 17, the phase informing unit 62b provides the clock generator 20 with the phase P0 of the sampling clock C0, from which the maximum difference D0_max has been obtained, as the phase data Cp (Step T1).
Consequently, the signal processing circuit 1b can adjust the phase of a sampling clock used for the sampling of the analog signal SA with higher accuracy than the above related technique [1] (the signal processing circuit 1a shown in FIG. 7) (refer to Patent Documents 2 to 4, for example).    [Patent Document 1] Japanese Patent Application Publication No. 2000-47649    [Patent Document 2] Japanese Patent Application Publication No. 2000-89709    [Patent Document 3] Japanese Patent Application Publication No. 2001-356729    [Patent Document 4] Japanese Patent Application Publication No. 2004-144842